They didn’t even respond to DF afaik.
DF must press them really hard to go on comparison side by side with XSX.
They didn’t even respond to DF afaik.
DF must press them really hard to go on comparison side by side with XSX.
Q&A available
Really good stuff here.
09:30PM EDT - Q&A Time
09:31PM EDT - Q: TDP? A: Not commenting. There’s so many things that are involved in the TDP, and tradeoffs. We’re not really able to descibe it without describing it in a technical environemtn
09:32PM EDT - Q: Can you stream into the GPU cache? A: Lots of programmable cache modes. Streaming modes, bypass modes, coherence modes.
09:33PM EDT - Q: Coherency CPU and GPU? A: GPU can snoop CPU, reverse requires software
09:35PM EDT - Q: Are you happy as DX12 as a low hardware API? A: DX12 is very versatile - we have some Xbox specific enhancements that power developers can use. But we try to have consistency between Xbox and PC. Divergence isn’t that good. But we work with developers when designing these chips so that their needs are met. Not heard many complains so far (as a silicon person!). We have a SMASH driver model. The games on the binaries implement the hardware layed out data that the GPU eats directly - it’s not a HAL layer abstraction. MS also re-writes the driver and smashes it together, we replace that and the firmware in the GPU. It’s significantly more efficient than the PC.
09:35PM EDT - Q: Is link between CPU and GPU clocks? A: Hardware is independent.
09:36PM EDT - Q: Is the CPU 3.8 GHz clock a continual or turbo? A: Continual.
09:36PM EDT - Continual to minimize variance
09:37PM EDT - Q: TSMC 7nm enhanced, is it N7P, N7+, or something else? A: It’s not base 7nm, it’s progressed over time. Lots of work between AMD and TSMC to hit our targets and what we needed
09:38PM EDT - Q: Says Zen 2 is server class, but you use L3 mobile class? A: Yeah our caches are different, but I won’t say any more, that’s more AMD.
09:39PM EDT - Q: With 20 channels GDDR6, is that really cheaper than 2 stacks HBM? A: We’re not religious about which DRAM tech to use. We needed the GPU to have a ton of bandwidth. Lots of channels allows for low latency requests to be serviced. HBM did have an MLC model thought about, but people voted with their feet and JEDEC decided not to go with it.
09:40PM EDT - Q: GDDR6 on sides, not bottom? A: bottom is power, how board interfaces with the chip. GPU has high EDC and currents, and you need clean copper to deliver that. With that much current you need to leave that space unless you use super expensive packaging. We did it the cost efficient way
09:41PM EDT - Q: Why do you need so much math for audio processing? A: 3D positional audio and spatial audio and real world spaces if you 300-400 audio sounds positional in 3D and want to start doing other effects on all samples, it gets very heavy compute. Imagine 20 people fighting in a cave and reflections with all sorts of noises
09:43PM EDT - That’s a wrap and we’re done for today. Come back tomorrow at 8:30am PT to talk about FPGAs. It’s 2:44am here in the UK, time to go to bed.
Simple calculation: 6.3-8.6 GigaRays/s.
2060Super: 6GRays/s & 2080Super: 8GRays/s
So…
Ms seemingly went all out on this console. Quite a turn over from xbone
It’s a monster and remember they couldn’t talk about everything cause there’s some NDA on juicy stuff, Cloud SOC and all.
Command Processor offloads the charge on the CPU to go on the GPU. Crazy possibilities so more power to the already beastly CPU.
The virtualization tech inside looks insane, lots of customization. They really went all out.
VRS full edge detail. No holes, warping, or checkerboard artifacts. Compatible with temporal AA tech.
Your turn Mark Cerny! When is the PS5 deep dive?
Don’t forget MS is also procuring the X chips for their (cloud) servers. Those chips will have lower yields so there should be plenty to enough to meet the demands of the S. Pricing is key here, and I believe they will adjust the price of the S based on these yields. The S could be closer in price if the yields are good on the X chips and there are less (but better quality) chips for the S. They would just be closer in spec also. If the yields are worse, then there are more but lower quality chips for the S and the price is lower.
Admittedly I have not done much research on yields, but it makes sense in theory I believe. Again it could also partially explain the wait on the announcement of the S. There might be some wiggle room in spec and price.
Oh I see, indeed X1 must have been the only home console to never be successfully hacked (though I believe in part due to it being open to develop for)
Can you elaborate on that? What stands E for
How many bits do they use in RGBA for every color?
This is interesting. Doesn’t seem like much of a difference between 6 & 8 but the 2060 and 2080S had very different performance results with RT. Hopefully it works out to be the latter for the Series X.
Also did someone talk about 20 GDDR6 channels?
We always thought Series X was 10 * 32 bit
But it seems to be 20 * 16 bit.
Or is it 20 because the 10 * 32bit interface is dual channel anyways?
They next big question is about 8*PCIe 4 Interface.
They use 2 * 2 channels for the internal and external SSD.
What do they use the other 4 channels for?
Is that all for the Soutbridge only, or some other stuff, too?
Its a floating point RGB with common 5-bit exponent. The fraction are 9-bit. Alpha, if used, is a separate 8-bit surface.
Yes! GDDR6 has a dual channel mode. The advantage is that each channel operates independently, so something that needs data urgently can wait less for a channel to be available.
Xbox Series X being N7+ is confirmed. But for PS5 we dont have any official confirmation. PS5 being N7+/N7P is more probable due to those high GPU clocks. But conversely Sony would have bragged about it if it was N7+. We just have to wait for another Cerny ASMR.
Microsoft has always been about pushing tech in the console space. It is great to see that they have once again done this. The Xbox One really is the one console that is an outlier.
nice live blog by anandtech there
they added extra texture sample modes for cases where not all mip levels are populated, which can often happen in SFS scenarios where texture parts are fetched asynchronous.
Thats not to bad.
Welcome to the forums by the way!
Maybe but I doubt it. Think about it, say the xsx SoC has yield of 60%, if they make 10 million of them thats 6million xsx chips and 4million xss chips, they would be in a situation with to many xsx chips.
Yet if the X has a yield of 60% and there is no S console at all, then the other 40% is essentially waste. Also compare this to say having separate X and S production lines where there will be waste on both lines.
It’s just a theory though, I don’t have the background to really push this one.